Operational amplifiers (OpAmps) in industrial and other high-voltage settings often operate at relatively high voltage levels, e.g. 15 VDC. Digital devices such as analog-to-digital converters (ADCs), however, typically operate at lower voltage levels, e.g. 3.3 VDC. This is problematical in that if the voltage of the output signal of the OpAmp is too high (e.g. 5-15 VDC) it can damage the electrostatic discharge (ESD) protection diode or other circuitry of the ADC.
Clamping circuits have been used to limit the output signals of OpAmps (“driver”) such so that they do not damage the ADCs or other low-voltage devices. Since the best performance of high-resolution ADC(s) (16 bits to 20 bits) is achieved when the input signal swings fully from rail to rail (e.g. from the positive power supply to the negative power supply of the ADC), the clamping circuits of the driver should be accurate, linear and low in noise. This has required relatively complex circuitry including feedback loops and feedback stabilization techniques in the past. In general, the driver performance (SNR+D) must be superior (>10 dB) to the ADC's, such that system performance is, for all practical purposes, limited by ADC only.
An example operational amplifier with clamping was manufactured by National Semiconductor of Santa Clara, Calif. (now a division of Texas Instruments, Inc. of Dallas Tex.) as part number CLC502. The CLC502 is an operational amplifier designed for low gain applications requiring output voltage clamping. This feature was accomplished by the use of a feedback loop including a number of external components to the OpAmp. As a result, the CLC502 is relatively expensive and complicated to implement due to the number and cost of the required external components to stabilize its feedback loop.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.